-----Original Message-----
From: Johannes Wolf [mailto:mp2100_at_mail-gw.estec.esa.nl]
Sent: Tuesday, July 09, 2002 11:09 AM
To: newtontalk_at_newtontalk.net
Subject: Re: [NTLK] New accelerator idea. needs no crystal. Need Help.
>Dear Mr. PCBman,
>I cannot agree in full to what you stated, because
>after looking into the reference manual I found
>that the internal core clock called DCLK is well synchronized to the bus
>interface domain clock MCLK if the processor is running in SnA mode.
>This mode eliminates the need of a second clock generator for the bus
>interface. So the MCLK is derived from the common 3,57 MHz CLK input.
>Since there is a PLL to generate the high frequency core clock, there is a
>fixed relation between DCLK and MCLK by definition.
>And the SA-110 is even able to switch the core clock between DCLK and MCLK
>(coprocessor register 15)
>And btw., I cannot see the point why this has been implemented if you cannot
>use it?
The point is not what is happening inside the SA-110, but its' relationship to things outside it. As DCLK and MCLK are
PLL'ed, they will of corse have a fixed relationship.
It is not this that I am referring to though. The 3.6864MHz (not 3.57 MHz) crystal drives the SA-110 and is multiplied
up. It also drives the voyager chips directly.
Just look and see that it connects to U6. If you change the PLL multiplier you change the SA-110's CCLK for sure but the
frequency of the clock into U6 is still 3.6864MHz.
Now you have destroyed the timing relationship between these chips.
Just becase a device has the CAPIBILLITY to do certain things deosn't mean that it will implemented in all systems.
>Since you can also control the ration between DCLK and MCLK (divide by 2 ..
>9)by means of the MCCFG setting, the IO clock can also be adjusted.
Yes, but in fixed steps that do not allow all posibillities.
>And now we are back to the question why this was not done in the first
>place:
>acording to the manual there are certain selection types for certain max.
>clock frequencies. It may be true that there was a financial aspect to chose
>the lower performance selection types or to be absolutely sure, maybe a
>power consumption aspect played a role as well ...
>And in my opinion: when we all agreed that it is possible to overclock the
>Newt "externally" why this should not work as well with changing the
>settings for the PLL???
Because changing the reference frequency ensures that all the rest of the system will follow until you reach the stops.
>From an engineering point of view this would be the smartest solution, would
>it not? But of course in the light of realization it is much more scary to
>diconnect and reconnect single pins from the SA-110...
No, it would not! Perhaps on the drawing board at the start of the project it could have been designed in but not as an
afterthought and especially without full schematics.
There are not too many people that would attempt this kind of modification. From an engineering point of view, simple is
best. I have a solution that involves none of this nonsense, dosen't use a crystal and is controlled by software. I am
still refining it and I am not ready to release it to the world yet, but when I do you can rest assured that it will be
a simple mod.
>I am looking forward to read your comment.
>Johannes
There it is.
Regards,
PCBman
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