Dear Mr. PCBman,
I cannot agree in full to what you stated, because
after looking into the reference manual I found
that the internal core clock called DCLK is well synchronized to the bus
interface domain clock MCLK if the processor is running in SnA mode.
This mode eliminates the need of a second clock generator for the bus
interface. So the MCLK is derived from the common 3,57 MHz CLK input.
Since there is a PLL to generate the high frequency core clock, there is a
fixed relation between DCLK and MCLK by definition.
And the SA-110 is even able to switch the core clock between DCLK and MCLK
(coprocessor register 15)
And btw., I cannot see the point why this has been implemented if you cannot
use it?
Since you can also control the ration between DCLK and MCLK (divide by 2 ..
9)by means of the MCCFG setting, the IO clock can also be adjusted.
And now we are back to the question why this was not done in the first
place:
acording to the manual there are certain selection types for certain max.
clock frequencies. It may be true that there was a financial aspect to chose
the lower performance selection types or to be absolutely sure, maybe a
power consumption aspect played a role as well ...
And in my opinion: when we all agreed that it is possible to overclock the
Newt "externally" why this should not work as well with changing the
settings for the PLL???
From an engineering point of view this would be the smartest solution, would
it not? But of course in the light of realization it is much more scary to
diconnect and reconnect single pins from the SA-110...
I am looking forward to read your comment.
Johannes
> -----Original Message-----
> From: newtontalk-bounce_at_newtontalk.net
> [mailto:newtontalk-bounce_at_newtontalk.net]On Behalf Of Humphreys, David
> (URB)
> Sent: Tuesday, July 09, 2002 4:29 PM
> To: 'newtontalk_at_newtontalk.net'
> Subject: Re: [NTLK] New accelerator idea. needs no crystal. Need Help.
>
>
>
>
> -----Original Message-----
> From: Andy Collins Sent: Tuesday, July 09, 2002 8:55 AM
>
> Hi Folks,
>
> I think I've come up with a different method of speeding up the MP2x00
> without needing to change the crystal...
>
> Oh dear! Don't do this! Quite apart from the exteme difficulty in
> isolating the pins, it won't work.
>
> It is true that the SA110 uses a PLL to multiply the crystal
> frequency. The multiplication factor is determined by the
> state of 4 pins on power up. If you change the level on these
> pins you will certainly change the core frequency. This is
> fine but the same crystal runs the voyager asic. It will still be
> running at its' 'normal' speed. This chip has more to
> do than just serial comms. There is a timing relationship between
> it and the SA-110 that is destroyed when you change
> the configuration pins.
> Changing the clock (crystal) frequency, on the other hand, keeps
> the system in 'lock-step'. From a system point of view,
> changing the main clock is the best way.
>
> Can the Newton be made to run at different speeds using the PLL
> muliplier pins?
> Yes - but it requires a lot more than just switching them.
>
> PCBman
>
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>
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