Hi Marco,
If the chip was designed by Apple I would assume that they did it right a
>made only the core frequency changable by these pins. If it is a standard
>PLL circuit it can be anything and we simply lack the schematics.
IIRC the StrongArm was originally designed by ARM, a spin-off from Acorn.
Yes, only the core frequency changed with these pins. The memory multiplier
is set by another 4 pins.
I don't know how
>exactly you know the meaning of the pins but switching the 2 to the power 6
>pin means a factor of 64 which would lead to 236MHz and maybe already exceed
>the capabilities of the processor.
>--
The SA110 data sheet shows a table giving values at the pins and the
corresponding internal clock speed.
I.e.
CCCFG CCLK Frequency in MHz (3.57-MHz Input) CCLK Frequency in MHz
(3.68-MHz Input)
0 85.7 88.3
1 92.7 95.6
2 96.4 99.4
3 103.5 106.7
4 139.2 143.5
5 146.4 150.9
6 157.1 161.9
7 164.2 169.3
8 185.6 191.3
9 196.3 202.4
10 207 213.4
11 221.3 228.1
12 235.5 242.8
13 249.9 257.6
14 267.8 276
15 278.4 287
Cheers.
Andy.
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