From: Konstantinos Xonis (Konstantinos.Xonis_at_physik.uni-giessen.de)
Date: Fri Jun 29 2001 - 06:42:59 PDT
Humphreys, David said (D) k
[...]
>
> The SA-110 has a device identification code register.
> No programmable supplementary identification code is provided.
>
> It's a 32-bit register.
>
> Bits 31 thru 28 carry the version
> Bits 27 thru 12 carry the part number
> Bits 11 thru 00 carry the JEDEC code
>
> Bits 27 thru 00 are always 0x102C06Bh
>
> So, despite the fact that the CPU has an ID number, it is the same
> for a particular version of the device and cannot serve as a unique
> identifier.
>
[...]
Hi David,
if I am allowed to throw in my $0.02 I'd like to say, that the
register You are refering to is not accessible from within running
code, it is the JTAG I/F ID-Register. The (Strong)ARM CPUs have
their ID Register implemented as Register 0 of Coprocessor 15
(System Control) which is defined as:
CP15R0,0 := { # Description of CPU-ID register
Implementor[31:24] : { 'D' : Digital,
'A' : ARM,
'I' : Intel,
},
ArchLevel[23:16] : { 0 : ARM ISA V3
1 : ARM ISA V4
5 : ARM ISA V5
},
PartNumber[15:4] : { # BCD Encoded PartNumber
},
MaskRevision[3:0] : { # Revision of Chip }
},
This is the one, taken into decision, which CPU we run on.
Hope that's not too off-topic.
Have a nice WeekEnd...
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