Konstantinos,
> if I am allowed to throw in my $0.02 I'd like to say, that the
> register You are referring to is not accessible from within running
> code, it is the JTAG I/F ID-Register.
True. This is part of the boundary-scan test interface. if it is to be used
then the nTRST pin is driven low then high. If it is not to be used,
it is tied low. If TCK is clocked, the ID will be clocked out of TDO.
The Newton may have this pin tied low, thus preventing this mode.
I do not claim to be a software guru but if you issued an IDCODE public
instruction,
would you not be able to read this register provided you issued
a EXTEST instruction?
The (Strong)ARM CPUs have
> their ID Register implemented as Register 0 of Coprocessor 15
> (System Control) which is defined as:
>
> CP15R0,0 := { # Description of CPU-ID register
> Implementor[31:24] : { 'D' : Digital,
> 'A' : ARM,
> 'I' : Intel,
> },
> ArchLevel[23:16] : { 0 : ARM ISA V3
> 1 : ARM ISA V4
> 5 : ARM ISA V5
> },
> PartNumber[15:4] : { # BCD Encoded PartNumber
> },
> MaskRevision[3:0] : { # Revision of Chip }
> },
>
> This is the one, taken into decision, which CPU we run on.
Again true. But for a given Manufacturer, Architecture level, part number
and rev. the number is the same, and is useless as a unique ID?
Regards,
David Humphreys
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